1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a metal-oxide-semiconductor (MOS) transistor.
2. Description of the Related Art
The basic structure of an MOS transistor comprises a gate, a source, and a drain. The gate further comprises a conductive layer and an oxide layer. Normally, the oxide layer includes silicon oxide (Si.sub.2 O). The source/drain is formed in the substrate in each side of the gate. Since the adhesion between the poly-silicon and the oxide is very strong, poly-silicon is used to form the conductive layer. However, to enhance the speed of date access, a well conductive layer is required. Therefore, a well conductive tungsten silicide layer is further formed on the poly-silicon layer. In addition, a well conductive source/drain is required too. As the devices become smaller and smaller, during the formation of conductive layer, a misalignment is easily to happen. Moreover, in the conventional method, forming a conductive layer on the gate and on the source/drain has to be performed separately.
To solve the above problems, in the conventional method, a process of forming a self-aligned silicide is used to form a titanium silicide (TiSi.sub.2) on the gate and the source/drain simultaneously. However, as the devices becomes smaller, it is more difficult to perform the self-aligned silicide process.
In the process of fabricating an MOS transistor, a spacer is formed on the side wall of the gate. A parasitic capacitance is inevitably produced.
FIG. 1A to FIG. 1B show a conventional method of fabricating an MOS transistor. In FIG. 1A, on the &lt;111&gt; plane of a p-type semiconductor substrate 10, an active region is defined. The active region is isolated by a device isolation structure 12, for example, a shallow trench isolation (STI).
In FIG. 1B, a gate oxide layer 14, for example, a silicon oxide layer having a thickness of about 100 .ANG. to 250 .ANG. is formed, for example, by thermal oxidation. On the gate oxide layer 14, a poly-silicon layer 16 having a thickness of about 2000 .ANG. to 3000 .ANG. is formed, for example by low pressure chemical vapor deposition (LPCVD). Using thermal diffusion or ion implantation, phosphorus ions or arsenic ions with a high concentration is doped into the poly-silicon layer 16 reduce the resistivity. While doping the poly-silicon layer 16, oxygen and phosphorus are reacted with poly-silicon to form a very thin (PSG) phosphorus silicate glass layer. To improve the adhesion between the doped poly-silicon layer 16 and the subsequent formed silicide layer, a solution containing hydrogen fluoride (HF) are used to remove the PSG layer. A photo-resist layer 20 is formed and patterned on the poly-silicon layer 16.
In FIG. 1C, using the photo-resist layer 20 as a mask, the poly-silicon layer 16 and the gate oxide layer 14 is etched to form a gate. Using sulfuric acid solution, the photoresist layer 20 is remove.
In FIG. 1D, using the doped poly-silicon layer 16 as a mask, the substrate 10 is lightly doped, for example, with phosphorus ions with a dosage of about 10.sup.13 /cm.sup.2 to form a lightly doped region 18.
In FIG. 1E, a dielectric layer, for example, silicon oxide, silicon nitride, or other similar material is formed on the substrate 10. The dielectric layer is anisotropically etched to form a spacer 24 on a side wall of the gate. Using the gate as a mask, the substrate is heavily doped, for example, with phosphorus ions or arsenic ions with a dosage of about 10.sup.15 /cm.sup.2 to form a source/drain 28. Since the spacer is formed by dielectric material, a parasitic capacitance is inevitably produced.
As the integration of devices increases, the resistance of source/drain is gradually increased to a value equivalent to the sheet resistance of channel. In FIG. 1F, a silicide layer, for example, a titanium silicide layer, is formed on the gate 16 and the source/drain 28. A conductive layer, for example, a titanium layer having a thickness of about 200 .ANG. to 1000 .ANG. formed by DC magnetron sputtering, is formed first. Under a proper temperature, the conductive layer is reactive with silicon to form a silicide layer 26 on the gate and a silicide layer on the source/drain 28. The remaining or the unreacted conductive layer is removed by wet etching.
As the size of devices shrinks, the parasitic capacitance becomes more and more obvious. To obtain an ultra-large scaled integration with a high operation speed and a low energy, the parasitic has to be minimized. In addition, the margin of short channel has to be increased to avoid short channel effect and punch through effect. Moreover, it is difficult to fabricate titanium salicide.